The present invention is related to testing processors, and more particularly to testing processors utilizing a probe mode.
Processors are continually designed with improved speed and capabilities compared to earlier designs. This results in complex processors with ever increasing instruction sets, registers, and caches. As the complexity of processors goes up, the amount of testing and debugging that is performed to maintain a reliable processor increases. This testing and debugging is also performed to improve the speed and efficiency of the processor.
A significant amount of debugging and performance enhancement is done before a processor can successfully be brought on the market. As the amount of debugging needed increases, the time before the finished product can be brought on the market increases. That precious time can be quite long with the current debugging methods.
The current debugging is tedious and time consuming. Testing hardware is usually required and is connected to the processor and puts the processor in a testing mode. Generally, a single instruction is executed and the results of that single execution are analyzed. The result of the execution is then compared to the expected results. For example, if the single instruction was to add xe2x80x9c2+2xe2x80x9d and put the result in a register and the instruction puts xe2x80x9c5xe2x80x9d in the register, an error has occurred. If the instruction puts xe2x80x9c4xe2x80x9d in the register, than an error has not occurred. Care is taken in selecting instructions to test the various aspects of the processor because only a limited number of instructions can feasibly be performed. Also, a user may be required to manually perform the testing and check for errors.
For relatively simple processors, only testing one instruction at a time may be sufficient for testing the processors. However, for more complex processors, only testing only one instruction at a time may not be sufficient to adequately test the processors. To execute more than one instruction or test instruction, each instruction must be loaded, executed and unloaded and then repeated for the next instruction. This xe2x80x9cstepping throughxe2x80x9d can be time consuming for complicated tasks or large number of instructions. Further, additional tasks may need to be performed in between executing each instruction to analyze information and results of executing the instruction.
Analyzing the information or results of an execution of an instruction can also be problematic with the current art of testing. The effect of one execution needs to be analyzed prior to executing another instruction. Furthermore, the current probe modes fail to provide access to all of the system registers and memory. Thus, the results of executing an instruction may not be seen and errors in the processor may not be detected.
The present invention addresses these and other issues associated with testing processors.
In one embodiment of the invention is a system including a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage unit. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.
Other systems and methods are disclosed.